Exploring Design Alternatives for a Highly-Integrated, Wide-Issue, Microprocessor-Based System

We present a methodology for comprehensively evaluating architectural and technological alternatives of the processor, cache hierarchy, system interconnect, and main memory subsystems. We use the methodology to explore the design of an 8-way superscalar microprocessor implemented in 0.3 micron technology and employed in a high-performance workstation. We discuss the cache hierarchy design challenges encountered with a highly-integrated wide-issue processor, and evaluate new approaches to multi-porting rst level data caches and pipelining large on-chip second level caches. Abstract: We present a methodology for comprehensively evaluating architectural and technological alternatives of the processor, cache hierarchy, system interconnect, and main memory subsystems. We use the methodology to explore the design of an 8-way superscalar microprocessor implemented in 0.3 micron technology and employed in a high-performance workstation. We discuss the cache hierarchy design challenges encountered with a highly-integrated wide-issue processor, and evaluate new approaches to multi-porting rst level data caches and pipelining large on-chip second level caches.